The invention relates to a design technology of semiconductor devices, and more particularly, to a pumping MOS (Metal Oxide Semiconductor) capacitor for pumping and decompression.
In general, a semiconductor memory device includes an internal voltage generation circuit for more efficient power use, in which internal voltages with various levels are generated. Examples of such internal voltages include a core voltage VCORE, a peripheral voltage VPERI, a pumping voltage VPP, a substrate bias voltage VBB, and so on, which are derived from a power supply voltage VDD provided from the outside and a ground voltage VSS.
Recently, as the level of each of the power supply voltage VDD and the ground voltage VSS decreases, there is a problem that the pumping voltage VPP derived from the power supply voltage VDD and the substrate bias voltage VBB derived from the ground voltage VSS become lower or higher than their respective target levels. This is because the pumping or decompressing capability of circuits for generating the pumping voltage VPP and the substrate bias voltage VBB was lowered.
As drawings to explain the above, FIG. 1 is a general pumping voltage VPP generation circuit and FIG. 2 is a general substrate bias voltage VBB generation circuit. Since these circuits are well-known in the art, the operation explanation thereof is omitted here.
Referring to FIGS. 1 and 2, it can be seen that each of the pumping voltage VPP generation circuit and the substrate bias voltage VBB generation circuit includes a plurality of pumping MOS capacitors CAP. Each of these circuits generates a pumping voltage VPP and a substrate bias voltage VBB by pumping or decompression through the pumping MOS capacitors CAP. In the following description, the pumping MOS capacitors CAP will be simply referred to as a “capacitor”.
FIG. 3 is a cross-sectional view of a capacitor CAP used for each of the pumping voltage VPP generation circuit and the substrate bias voltage VBB generation circuit.
Referring to FIG. 3, the capacitor CAP is manufactured in a MOS form, and includes a substrate 11 on which an N well is formed, a dielectric film 12 formed on the substrate 11, a gate 13 formed on the dielectric film 12, and an N-type source and drain 14 (also called a pick up well) formed on both sides of the gate 13 on the substrate. Here, the gate 13 corresponds to one side electrode of the capacitor CAP, and the N well and the N-type source and drain 14 correspond to the other side electrode thereof.
When the level of each of the power supply voltage VDD and the ground voltage VSS decrease as noted above, the pumping voltage VPP generation circuit or the substrate bias voltage VBB generation circuit increases an electrode area of the capacitor CAP, thereby improving pumping or decompressing capability.
As a result, the area occupied by the capacitor CAP within the generation circuit is increased, which means an increase in a chip size. Thus, the number of net dies that can be produced per wafer is decreased, thereby increasing manufacturing costs.
Therefore, there is a need for a technology capable of improving pumping or decompression capability of the pumping voltage VPP generation circuit or the substrate bias voltage VBB generation circuit by increasing capacitance of the capacitor CAP, without an increase in a chip size.